| 摘要 |
PURPOSE:To decrease the delay time in a gate drive circuit output signal to a control signal by setting an FF circuit at the leading pulse of the control signal and resetting the circuit at the trailing pulse. CONSTITUTION:The control signal is fed to pulse transformers 27, 28 via the FF circuits 21, 22, an EX-OR circuit 25, AND circuits 23, 24 and FETs 25, 26. Thus, a pulse transformer 27 generates a pulse at the leading of the control signal and the pulse transformer 28 generates a pulse at the trailing of the control signal. Then the FF circuit comprising the FETs 2, 3 and resistors 6-11 is reset by an output pulse of the pulse transformer 27 and reset by the output pulse of the pulse transformer 28. The output of the FF circuit is given to a gate of the FET17 in such way. Thus, the delay time of the output signal of the gate drive circuit to the control signal is decreased. |
