| 摘要 |
PURPOSE:To release abnormal operations of a CPU so as to prevent wrong outputs, by resetting the CPU to its initial state when the 1st data readout signal and 2nd data readout signal or write signal are simultaneously generated. CONSTITUTION:When the 1st data readout signal and 2nd data readout signal are simultaneously outputted due to abnormal operations of a CPU1, a transistor 24 is set to an interrupted state because the level of the output terminal the inverse PSEN becomes low. Moreover, the level of the output terminal of inverse RD also becomes low low and the output of an NOR circuit 20 becomes high in level and, as a result, a transistor 23 is set from an interrupted state to active state. Therefore, an electric current is made to flow to the transistor 23 and the terminal voltage of a capacitor 17 gradually drops. When the terminal voltage of the capacitor 17 drops lower than the threshold voltage Vs1 of an inverter 14, the output of an inverter 19 becomes high in level and the CPU1 is reset to the initial state. |
