| 摘要 |
PURPOSE:To decrease the development period of a semiconductor integrated circuit of the master slice system by using a basic cell where two pins among input points are connected to a common and a power supply and other inputs are used for logical NAND or NOR. CONSTITUTION:In connecting a terminal C to a common and a terminal D to a power supply, a 2-input NAND circuit is obtained, where terminals A, B are used as inputs and a terminal E is used as an output. Further, in connecting the terminals A, B to form a connecting point F, an inverter is obtained, where the terminal E is used as the output and the point F is used as the input. Various logical gates are realized by connecting the terminals with proper combination and various logical circuits are constituted by using the said logical gate. For example, a tri-state gate is obtained where the output E shows a high impedance with an input EN logical '0', and the output E gives an OR output between the two inputs A, B with the input EN being logical 1, by connecting respectively the input/output terminals of the inverter comprising the said basic cell to the terminals C, D of the basic cell respectively. |
