| 摘要 |
PURPOSE:To shorten interpreter execution time by means of a largescale logical circuit simulation, by performing processing by interpreting the reverse polish notation outputted by a compiler as input information. CONSTITUTION:When an address value is fetched by a main storage device MM3 from an address calculating circuit 1 through a bus ABUS2, the reverse polish code stored in the address designated by the address value is fetched by a decoder DECO5 through a data bus DBUS4. The DECO5 decodes the reverse polish code and sends a signal '1' to one of output buses A. A timing control circuit 6 actuates the address calculating circuit 1 and an arithmetic circuit 7 in accordance with the signal from the output buses A.
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