发明名称 SELECTION CIRCUIT FOR DATA PROCESSOR
摘要 PURPOSE:To facilitate easy control of a selection signal producing part by defining the data including a bit indicating the validity of the data as a subject of selection. CONSTITUTION:For instance, the number (n) of bits is equal to 4 with three data A, B and C. Under such conditions, a valid bit selecting circuit 11 supplies the selection information S (=sa, sb, sc) and a valid indication bit ae of data A (=ae, a0, a1, a2) together with a valid indication bit be of data B (=be, b0, b1, b2) and a valid indication bit ce of data C (=ce, c0, c1, c2). Then the circuit 11 outputs a logic equation de=sa.ae+sb.be+sc.ce through a valid indication bit de. A data selecting circuit 12 supplies the information S together with bits a0, b0, c0 in said data A-C and valid indication bits ae, be and ce respectively and outputs a bit data d0 with which a logic equation d0=sa.ae.a0+sb.beb0+ sc.ce.c0 is satisfied.
申请公布号 JPS6198440(A) 申请公布日期 1986.05.16
申请号 JP19840218682 申请日期 1984.10.19
申请人 NEC CORP 发明人 ISHIZUKA TERU
分类号 G06F7/00 主分类号 G06F7/00
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