| 摘要 |
<p>PURPOSE:To avoid unnecessary prediochronous control by executing a sampling of a write address signal to detect the presence of necessity of prediochronous slip control while avoiding a signal value uncertainty time zone produced when the said signal changes. CONSTITUTION:A signal obtained by inverting a write address change detection signal 32 at a NOT circuit 326 is delayed by a delay circuit 327 at a time slightly shorter time than the write cycle time to obtain a sampling aperture signal. When an address check timing signal 313 is generated near the change in the write address cycle, that is, at a time band or its vicinity when the write address signal 14 is uncertain, the address check timing 313 is generated at a positive logical time zone of the sample aperture signal to execute prediochronous slip control.</p> |
