| 摘要 |
PCT No. PCT/JP80/00124 Sec. 371 Date Feb. 5, 1981 Sec. 102(e) Date Jan. 28, 1981 PCT Filed Jun. 4, 1980 PCT Pub. No. WO80/02773 PCT Pub. Date Dec. 11, 1980.An MOS device including a substrate bias generating circuit, comprising: a clock generator for receiving an external clock signal and generating first and second internal clock signals; an internal circuit operated by the first and second internal clock signals; a pumping circuit driver for generating third and fourth internal clock signals in synchronization with the first and second internal clock signals and; a pumping circuit operated by the third and fourth internal clock signals. In this device, when the substrate potential (VBB) is relatively high, currents flow from the substrate to the pumping circuit. |
