发明名称 TIMING ADJUSTING CIRCUIT
摘要 <p>PURPOSE:To prevent a storage device using a timing adjusting circuit previously from the generation of an error output and to improve the reliability of the device by checking the output part of a decoding circuit under the output stopped status of a timing signal generating circuit to detect a failure. CONSTITUTION:Four delay elements 21-24 are connected in series to the output of the timing signal generating circuit 1, the outputs of respective delay elements 21-24 are inputted to one input of each of selecting gate circuits 31-34 and the outputs of a decoding circuit 5 which are obtained from an input through a selection control signal input terminal 4 are the other inputs of said selecting gate circuits 31-34. Respective outputs of the selecting gate circuits 31-34 are connected to a storage element group M through an OR circuit 6 and a timing signal 7 is outputted from the element group M. In addition, the output of the circuit 1 is branched and connected to an inable terminal of the decoding circuit 5 to control the circuit 5 and a failure detecting signal 91 of the decoding circuit is outputted from the output of an AND circuit 9 to a terminal 10 through an OR circuit 8.</p>
申请公布号 JPS6120113(A) 申请公布日期 1986.01.28
申请号 JP19840140208 申请日期 1984.07.06
申请人 NIPPON DENKI KK 发明人 OKUYA TOKUNORI
分类号 G11B5/09;G06F1/04;G06F1/06;G11B20/10 主分类号 G11B5/09
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