| 摘要 |
PURPOSE:To prevent oscillation of a circuit at the absence of a digital signal by detecting the digital signal and applying a clock signal to a circuit discriminating and reading logical '1' or '0' in place of the digital signal when no digital signal exists. CONSTITUTION:An input terminal 1 of the digital signal reader 7 is provided with a detection circuit 40 detecting whether or not the digital signal is inputted with a prescribed state and the output changes over a switch 41. The switch 41 outputs selectively alternatively either a master clock signal fed from an inverse amplifier consisting of an inverter 42, and resistors 43, 44 or a digital signal fed from an inverter 10. A resistor 45 and a capacitor 46 constitute a low-pass filter. When the switch 41 is thrown to the position of the inverter 42, a master clock outputted, it is compared with a reference value by an inverter 13 to lock a PLL circuit 6 of the post-stage by using the clock signal. |
