发明名称 |
Semiconductor device monolithically comprising a V-MOSFET and bipolar transistor isolated from each other |
摘要 |
A semiconductor device comprising a high voltage withstanding vertical MOSFET and a low voltage withstanding element both formed on a single chip. A buried layer of a high impurity concentration is formed in a region where the vertical MOSFET is formed, and another buried layer of a high impurity concentration is formed in a region where the low voltage withstanding element is formed. These buried layers have different thickness, whereby the series resistance of a circuit adjacent to the vertical MOSFET is reduced without lowering the withstand voltage of the vertical MOSFET.
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申请公布号 |
US4589004(A) |
申请公布日期 |
1986.05.13 |
申请号 |
US19840665506 |
申请日期 |
1984.10.30 |
申请人 |
TOKYO SHIBAURA DENKI KABUSHIKI KAISHA |
发明人 |
YASUDA, SEIJI;YONEZAWA, TOSHIO;HIRAKI, SHUNICHI;MIYAGAWA, MASAFUMI |
分类号 |
H01L21/74;H01L21/761;H01L21/8249;H01L27/06;H01L29/08;H01L29/78;(IPC1-7):H01L29/78;H01L27/02 |
主分类号 |
H01L21/74 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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