| 摘要 |
PURPOSE:To obtain a semiconductor memory element having the high degree of integration by forming a P<+>N<+> junction to the lower section of a source diffusion layer and fixing a source layer at the substrate potential of an Si substrate. CONSTITUTION:Field regions 1 and word lines 2 are superposed on a P<-> Si substrate 9 through a normal NMOS process, floating gates 4 are shaped. P ions are implanted, and N<+> type source-drain layers 3, 7 are formed through heat treatment. When a resist mask 11 is applied and B ions are introduced just under the source layer 3 and a P<+> layer 10 is formed through heat treatment, a semiconductor memory element displays Zener diode characteristics at not more than several V withstanding voltage. When concentration is further increased and a diffusion is inhibited, withstanding voltage can be reduced to approximately 0.5-1V, the element displays tunnel diode characteristics, and withstanding voltage often extends over approximately 0V. Accordingly, the potential of the source layer 3 can be operated by controlling the junction characteristics of the P<+> layer 3 and the N<+> layer 10 without using a bit line 6 and a connecting hole 5. The allowance of mask alignment is also unnecessitated, thus improving the degree of integration. |
