Non-volatile piezoelectric memory transistor

摘要

A piezoelectric double diffusion MOS structure in which three gates are inserted in the CVD oxide element. These gates are overlapped layers of CVD polysilicon on top of the ZnO and are capacitively coupled to the silicon substrate. The charge is placed on the middle floating gate and is retained because of the oxide layers which separate the gates. A program erase, gate is provided for discharging the floating gate and to set the modes.