发明名称 |
Mechanism for implementing one machine cycle executable trap instructions in a primitive instruction set computing system |
摘要 |
A mechanism for performing a run-time storage address validity check within one machine cycle. The mechanism, functioning together with an intelligent compiler, eliminates the need for hardware implementation of a storage validity check. More particularly, the mechanism performs its function in one machine cycle in the event that a trap exception does not cause an interrupt. In the rare instance when an interrupt is necessary, a number of machine cycles will be impacted. The mechanism comprises a minimum amount of logic circuitry for determining the trap condition operating in conjunction with conventional, previously existing compare, branch instruction testing, and interrupt generation circuitry.
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申请公布号 |
US4589065(A) |
申请公布日期 |
1986.05.13 |
申请号 |
US19830509733 |
申请日期 |
1983.06.30 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
AUSLANDER, MARC A.;COCKE, JOHN;HAO, HSIEH T.;MARKSTEIN, PETER W.;RADIN, GEORGE |
分类号 |
G06F9/45;G06F9/30;G06F9/32;G06F9/48;(IPC1-7):G06F9/00 |
主分类号 |
G06F9/45 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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