| 摘要 |
<p>PURPOSE:To solve the incapability of the 1-bit shift produced when the working speed is increased with a VRAM incorporating the shift register of the 1-word segment containing the master-slave constitution of each stage, by dividing the shift register into plural columns. CONSTITUTION:Transfer gates T3 and T4 are added to attain the connection of odd colum SR1, SR3,... and even column SR2, SR4,... of a shift register to the odd and even bit lines respectively. In the same way, the dummy cells DC are also connected to the odd and even bits. The transfer gates T1-T4 are selected by exclusive transfer clocks TR1 and TR2. That is, the gates T3 and T4 are turned on by setting clocks TR2 and TR1 at H and L respectively. Then the odd bit lines are connected to columns SR2, SR4,... together with the even bit lines connected to columns SR1, SR3,... respectively (reverse mode). Thus the incapability of the 1-bit shift can be solved in said reverse mode.</p> |
