| 摘要 |
<p>An interface circuit for coupling a parallel data device to a serial data channel over which Manchestertype codes are transmitted. In the interface circuit, an efficient and reliable Manchester decoder comprising a flip-flop an exclusive-or gate and at least one delay line separates the data and clocking signals. The serial data signals are clocked into a serial register under control of the external clocking signals from the channel. A carrier detector enables the serial register only when valid information signals are present. A parallel data register receives in parallel the data from the serial data register. To get in phase the external clocking signals with the internal clock source, an internal clock synchronizing circuit recycles the internal clock source upon the occurrence of a synchronizing character that is transmitted over the serial data channel. In this fashion, the internal operations of the parallel data transfers are in phase, but isolated from the external clocking signals so that in the event that the external clocking signals become corrupted due to noise or simultaneous transmissions of information signals by different devices, the internal parallel transfer operations may continue freely without disruption.</p> |
