| 摘要 |
A residue to analog converter associated with residue numbers {m1,m2,m3} of the residue number system defined by the moduli set {p1=2n-1, p2=2n, p3=2n+1} and which does not require memory comprises five standard binary adder circuits, apparatus for performing multiplication by bit shifting, and a modulo p1 p3 adder circuit. First and second binary adders combine the residue signals m1 and m3 to produce sum and difference signals which are bit shifted by grounding 2n-1 and n-1 lines, respectively, and locating them as less significant bit lines ahead of these sum and difference signal lines. A modulo p1*p3 adder sums these bit shifted signals. A third binary adder, which ignores overflow, performs a modulo p2=2n subtraction of m2 from the n less significant bits of the modulo p1*p3 sum signal to produce a second difference signal. This second difference signal is bit shifted by 2n grounded lines that are connected as less significant bit lines ahead of this signal, and then subtracted from this bit shifted signal in a fourth binary adder to produce a correction signal. The modulo p1*p3 sum signal and the correction signal are summed in a fifth binary adder to produce a three dimensional binary signal r(m1,m2,m3) that is representative of a residue signal {m1,m2,m3}. The corresponding analog signal is produced with a standard D/A converter. Structure for implementing the modulo p1*p3 adder circuit with adders that are all standard binary adders is disclosed.
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