| 摘要 |
Additional logical structures are respectively interactive with either an edge-triggered dual D-type flip-flop or an edge-triggered J-K flip-flop in order that each such flip-flop may be fully scan-set testable in all the elements thereof. Two scan-set test enabling signals, as well as two scan-set clock signal, are used to conduct three tests, as well as enabling normal edge-triggered operation. The three tests enable scan-set testability of the totality of the edge-triggered flip-flop. Two of the tests characteristically cause the logical interconnection of tested logical elements as inverter strings, which inverter strings are merged into the scan-set test loops. In addition to supporting functional logical verification, the inverter strings support the evaluation of propagation time upon such strings in order to determine the operational speed and/or impedance environment of the tested flip-flops. Marginal, as well as failed, flip-flops (flip-flop environments) are identifiable.
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