发明名称 CERAMIC DUAL IN-LINE PACKAGE (CERDIP) INTEGRATED CIRCUIT
摘要 PURPOSE:To prevent the generation of a purple plague due to the heat history of sealing by a method wherein a gold eutectic alloy layer is formed on the gold-metallized layer formed on a ceramic substrate, and an outer lead and the gold eutectic alloy layer are connected to an aluminum fine wire. CONSTITUTION:A gold-metallized layer 22 is formed on the center recessed part of a ceramic substrate 21, an IC chip 23 is rubbed against the layer 22, and a gold-silicon eutectic alloy 25 is grown and fixed. At this time, the gold- silicon eutectic alloy 25 is to be formed as far as to the point where a wire connection is performed on the gold-metallized layer 22. Then, each electrode of the IC chip 23 and a substrate potential are connected to an outer lead 27 using aluminum fine wires 26 and 26'. Subsequently, a ceramic cap 28 is adhered to the ceramic substrate using a low melting point glass 29, and the IC chip 23 is airtightly sealed.
申请公布号 JPS6191941(A) 申请公布日期 1986.05.10
申请号 JP19840213844 申请日期 1984.10.12
申请人 NEC CORP 发明人 KANEDA KENICHI
分类号 H01L21/52;H01L21/58;H01L21/60 主分类号 H01L21/52
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