| 摘要 |
PURPOSE:To transmit a large amount of data at a high speed by performing data communication between plural data processing means through an interposing storage means. CONSTITUTION:A switching signal is outputted from the access output part 1c of the 1st CPU1 (steps 101 and 102) and the 1st data separator 5 is operated through a delay circuit 7 to connect the data input/output part 4b of a RAM4 to the 1st data input/output part 1b. Then, the data o the 1st CPU is stored in a RAM4 (steps 103-105) and then the 2nd data separator 6 is operated to connected the RAM4 to the 2nd CPU2 (steps 106). The 2nd CPU2 after finishing arithmetic processing enters an interruption permit state (step 201). The data stored in the RAM4 is read in the 2nd CPU2 (steps 202-204). When the 2nd CPU2 enters an arithmetic state, an interruption inhibition state is entered (step 205). |
