| 摘要 |
<p>PURPOSE:To attain ease of timing extraction by selecting properly an information bit block length (n), the same polarity signal (m), and an M-series generator reset period to suppress the consecutive same polarity signals as transmission line signals to a prescribed number or below. CONSTITUTION:A speed conversion circuit 12 inserts an excess bit to an input information signal. A same polarity signal counter circuit 13 compares an output information bit of the circuit 12 with an output of the M series generator 15 at each n bits in advance, and when it is estimated that consecutive same polarity signals of >=m bits are included in a signal after both signals are exclusively ORed through the comparison between an output information bit of the circuit 12 and an output of the M series generator 15 at each n bits in advance, an inhibition signal 17 is transmitted to a gate circuit 16 to inhibit an output 18 of the M series generating circuit from being fed to an exclusive OR circuit 14. The output of the circuit 13 is given to an excess bit control circuit 19, and this circuit gives it to an excess bit inserted at each n bits of the output of the circuit 14 as the information that the M series and the information signal are not exclusively ORed. The reset pulse period fed to the M series generator 15 via an input terminal 20 is used as the frame synchronizing pulse period or the n-bit period.</p> |
