| 摘要 |
PURPOSE:To decrease the transmission delay time and memory capacity by providing an interleaving circuit converting periodically the arrangement of a data signal within the same period as an error correction circuit in a data terminator by a 2-wire time division direction control system. CONSTITUTION:A buffer circuit 14 of a transmission section transfers memory content to the interleaving circuit 15 when a bit number corresponding to a burst length is stored. In this case, adjacent bits in the circuit 15 are stored in a location apart by n bits. Each bit in the circuit 15 is transmitted from a terminal 17. The inputted burst signal waveform at the reception side is stored in a buffer circuit 22 according to a reception burst timing signal. After the end of reception of one burst, the content of the circuit 22 is subjected to deinterleaving by a deinterleaving circuit 24. The circuit 24 outputs the interleaved signal to an error correction circuit 25 and a syndrome generating circuit 26 in the unit of code blocks. When the circuit 26 detects an error, it generates an address signal of the erroneous time slot. The circuit 25 uses this signal for error correction. |
