| 摘要 |
PURPOSE:To make a complicated circuit unnecessary by adding alternately a signal of logical levels '1' and '0' in accordance with either of plural clocks to an incoming line when a channel is set, and selecting and adding one of plural clocks to a two-bit shift register of an outgoing line so that two outputs may always indicate a different logical level. CONSTITUTION:When a channel is set in a channel switch 200, a control circuit adds a control signal to a terminal 110, sets a selector 102 to a test mode, and sends, to the set channel, the signal (signal in which logical levels '1' and '0' appear alternately) which divides the clock signal supplied from a clock source 222 by a latch circuit 101. The control circuit adds a change-over signal of a switch 122 of a variable delay circuit 103 to a terminal 113, changes a phase of a clock added to a two-bit shift register 104, signal patterns '0' and '1' or '1' and '0' appear at the two-bit shift register 104 by the phase relation of the signal sent to an outgoing line 213 and the clock from a variable delay circuit 103, and at such a time, the condition of the variable delay circuit 103 is maintained. |
