发明名称 BIT REDUCTION SYSTEM
摘要 <p>PURPOSE:To make it unnecessary to change the constitution of a memory in accordance with the rate of bit reduction and to simplify the control by setting one frame memory to the second mode to transfer data from this memory to the other memory while the other frame memory is set to the first mode. CONSTITUTION:Switch circuits 14 and 17 are connectecd to sides of contacts (a) and (b) by a switching signal from a timing generating circuit 21; and if a frame memory 15 is in the write mode and a frame memory 16 is in the read mode, digital data from the memory 16 is transferred to the memory 15 while the frame memory 15 is in the write mode, and thereby, bit reduction data is received simultaneously in the constitution having two frame memories and is syntherized, and thus, the control operation and the circuit the constitu tion of memories in accordance with the rate of bit reduction.</p>
申请公布号 JPS6189756(A) 申请公布日期 1986.05.07
申请号 JP19840210982 申请日期 1984.10.08
申请人 SONY CORP 发明人 MIYABE YUTAKA
分类号 H04N19/00;H04L13/08;H04L23/00;(IPC1-7):H04L13/08;H04N7/13 主分类号 H04N19/00
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