| 摘要 |
<p>PURPOSE:To detect an abnormal condition due to a noise, etc., as an error and to improve reliability with a simple composition by installing a circuit which compares and collates an output signal of the first and third FF. CONSTITUTION:A reading signal A is fetched by the first clock B at the first FF7 of a data reading circuit, and reset by the second clock C after the data are recognized. The second FF8 is set by the signal A and reset by a timing signal D after the data are recognized. An output G of the FF8 is added to the third FF9, set by the third clock E and reset by the clock C. An output F of the FF7 is added to AND gates 10 and 13 and an output F' is added to an AND gate 11. An output H' of FF9 is added to gates 10 and 11 and an output H' is added to the gate 13. When a check timing K occurs, the output signal of FFs 7 and 9 is compared and collated at the gates 10, 11 and 13 and an OR gate 12, and the abnormal condition due to a noise, etc., is detected.</p> |
