| 摘要 |
A flip-flop circuit receives a portion of a multiple bit output from a combinational logic circuit to be tested, and feeds back a plurality of bits to comprise a portion of the multiple bit input to the combinational logic circuit. The flip-flop circuit includes a plurality of master and slave flip-flops with the master flip-flops being operable in parallel to receive the output from the combinational logic circuit or in series as a shift register, and the slave flip-flops being operable either in parallel to receive outputs from the master flip-flops or in series as a shift register. The occurrence of a fault in a combinational logic circuit can be determined by examining the contents of either the master or slave flip-flops at a particular clock cycle. |
