| 摘要 |
PURPOSE:To facilitate a file control by matching an address in buffer memory to a specific scan period during a vertical blanking inverval, and writing a specific code in said memory during a horizontal period when a data signal is not overlapped. CONSTITUTION:A data latch drive circuit 11, upper-order address generator circuit 20 and lower-order address generator circuit 19 are operable in a period when a gata signal arises. An address switching circuit 15 connects outputs of the circuits 19 and 20 to an address in a buffer memory 16. The circuit 20 counts horizontal synchronizing signals from an input terminal 18, while the circuit 19 counts clock signals from an input terminal 10. For instance, when a character signal is overlapped, a signal arises from a framing code detection circuit 14. By said signal and the clock signal, the data latch drive circuit 11 drives a data latch circuit 13, while the character signal is written in the memory 16. When the character signal is not overlapped, an ''FF'' code is written in the memory 16. |
