发明名称 GATE ARRAY MASTER SLICE IC DEVICE
摘要 PURPOSE:To improve the characteristic of signal transmission speed, etc. and increase the integration degree while keeping the wiring redundancy of wiring channel regions by mixing one-column type basic cell arrays capable of unit cell wiring on any side and two-column type basic cell arrays restricted in unit cell wiring. CONSTITUTION:A two-column type basic cell array BC2 is provided between one-column type basic cell arrays BC1. A wiring channel region CH is provided on the outside of the two-column type basic cell array BC2, but no wiring channel region exists between each of one-column type basic cell arrays BC1-1 and BC1-2 in that array BC2; besides, these arrays BC1-1 and BC1-2 are arranged in right-left symmetry. Therefore, the restriction in use of wiring channel regions of the arrays BC2 can be sufficiently compensated because the arrays BC1 can select any of wiring channel regions.
申请公布号 JPS6184847(A) 申请公布日期 1986.04.30
申请号 JP19840206144 申请日期 1984.10.03
申请人 FUJITSU LTD 发明人 TAKAYAMA YOSHIHISA;FUJII SHIGERU
分类号 H01L21/822;H01L21/82;H01L27/04;H01L27/118 主分类号 H01L21/822
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