发明名称 SEQUENCE CONTROL CIRCUIT
摘要 PURPOSE:To handle easily the abnormal processing by cascade-connecting FFs corresponding to the man-hour in a ring shape by means of interposing a delay means between FFs. CONSTITUTION:A sequence control circuit 15 is provided with RS.FFs19 corresponding to the man-hour, and a man-hour checking timer 20 is interposed as a delay means between the RS.FFs, whereby FFs19 are cascade-connected in a ring shape. Thus when an electric power source is turned on, a power-on reset signal P.ON.R is generated. The FF19 in a step 1 is set, while FFs 19 in other steps are reset through an OR gate 21. When jump conditions are not satisfied and only jogging conditions are satisfied, the man-hour checking timer 20 in the posterior stage starts its action after the setting. When the jogging conditions are satisfied after setting the set time, the FF19 in a step 2 is set, while the FF19 in the step 1 is reset. Afterwards the similar action is repeated.
申请公布号 JPS6184704(A) 申请公布日期 1986.04.30
申请号 JP19840206286 申请日期 1984.10.03
申请人 HITACHI LTD 发明人 ONISHI HIDEO;YAMAMOTO AKIRA;SATO HIROTAKA;KOIWAI JUICHI
分类号 G05B19/05;G05B19/02;(IPC1-7):G05B19/02 主分类号 G05B19/05
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