发明名称 TRANSFER CONTROL SYSTEM
摘要 PURPOSE:To improve the data transfer capability of a multiplexer channel by constituting the processing time required for data transfer to be constant independently of the transfer byte width. CONSTITUTION:The transfer byte width (m) in a microprogram is set to a byte request register 7 to apply initializing processing of a local counter 8 and setting of a byte counter register 9. When data is transferred with an input/ output device 12-i, the count of the local counter 8 is counted up at each 1 byte transfer, compared with a value of the byte request register 7 and when they are coincident, the next transfer processing request CHREQ is issued to the microprogram and the value of the byte counter register 9 is decreased by the count of the local counter 8. The byte counter is referenced at the microprogram side to prepare for the next transfer.
申请公布号 JPS6182261(A) 申请公布日期 1986.04.25
申请号 JP19840190339 申请日期 1984.09.11
申请人 FUJITSU LTD 发明人 SHIOYA KATSUHIKO
分类号 G06F13/12;G06F13/38 主分类号 G06F13/12
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