| 摘要 |
PURPOSE:To obtain a request signal reception circuit whose priority is changed as required by using an order decision circuit and a selection circuit setting priority of plural request circuits in plural ways. CONSTITUTION:When a request signal 117 is received, a signal outputted from a terminal Q of an F/F101 inhibits an AND gate 110 to inhibit the reception of a request signal 118 and when the request signal 118 is received, a signal outputted from a terminal Q' of an F/F101 inhibits an AND gate 109 to inhibit the reception of the request signal 117. When the request signals 117, 118 are compete, a signal of H level is outputted from the terminal Q of the F/F101 before a signal of L level is outputted from the terminal Q' of the F/F104 to inhibit the AND gate 110, then the request signal 117 is received with priority. When the signal of L level is outputted from a timer 106, the priority is reversed. |
