| 摘要 |
<p>PURPOSE:To execute a high speed reading in the two-way direction by outputting serially the output signal of a sense amplifier in a dynamic type RAM in accordance with the shifting action of a two-way shift register. CONSTITUTION:When address signals A0-A8 are supplied at a low level together with a chip selecting signal inversion CS and a refreshing control signal inversion RESH, a memory condition of the memory cell connected to the word line designated by this result is amplified by a sense amplifier SA. A static type memory cell SRAM receives an amplifier output in parallel. Since a shift lock phirs is supplied to a shift register SR, SR successively shifts a logical '1' signal set in accordance with the shift direction. Since the memory cell SRAM is successively selected in accordance with the shifting action, the reading signal is serially sent through a main amplifier MA and a data output buffer DOB. The shift direction of the shift register SR is set in the down to up/up to down directions in the figure by the low level/high level of a write enable signal inversion WE.</p> |
