发明名称 Circuit arrangement for telecommunications systems, in particular telephone switching systems, with input/output processors interacting via bus lines with central data processing systems
摘要 If the operating voltage of a processor fails, the latter completes a currently running bus cycle of a data exchange process with an input/output device using the power stored in a blocking capacitor. De-activation of the processor on the basis of coincidence of failure signal and bus cycle end signal. <IMAGE>
申请公布号 DE3438494(A1) 申请公布日期 1986.04.24
申请号 DE19843438494 申请日期 1984.10.19
申请人 SIEMENS AG 发明人 EHER,MANFRED,ING.
分类号 G06F1/30;(IPC1-7):G06F1/00;H04Q3/44 主分类号 G06F1/30
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