发明名称 MOS COMPARATOR CIRCUIT SUITABLE FOR MONOLITHIC INTEGRATION
摘要 <p>A circuit of a monolithically integrable MOS-comparator has a capacitor, a signal input and a reference input of the comparator being alternatingly connected to the capacitor via respective first and second clock-controlled transfer transistors, a first amplifier stage having a control input and an output, the capacitor being directly connected to the control input and being also connected via a third transfer transistor to the output of the first amplifier stage, a second amplifier stage having a control input and an output, the output of the first amplifier stage being further connected via a fourth transfer transistor to the control input of the second amplifier stage. A third amplifier stage identical with the first and second amplifier stages has a signal input and an output, the output of the second amplifier stage being a first signal output of the comparator and being also connected to the signal input of the third amplifier stage. The output of the third amplifier stage as a second signal output of the comparator and as connected via a fifth transfer transistor to the control input of the second amplifier stage. Means for transmitting two clock signals are connected to the first and second transfer transistors, respectively, for alternatingly switching the signal input and the reference input, respectively, of the comparator to the capacitor, the signal-transmitting means being also connected to the third, fourth and fifth transfer transistors for controlling the same.</p>
申请公布号 EP0071265(B1) 申请公布日期 1986.04.23
申请号 EP19820106842 申请日期 1982.07.28
申请人 SIEMENS AKTIENGESELLSCHAFT 发明人 REINER, ROBERT, DIPL.-ING.
分类号 H03M1/36;G01R19/165;H03K5/08;H03K5/24;H03M1/00;(IPC1-7):G01R19/165 主分类号 H03M1/36
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