| 摘要 |
PURPOSE:To suppress the increase in the scale of the circuit as the number of tracks increases by allowing one frame address counter to serve as frame address counters each provided for one track. CONSTITUTION:Synchronizing signals x1, x2...xn of respective tracks which are detected by frame synchronism detectors 31, 32...3n are added together by a synchronous gate 90 (OR gate), whose output pulse train is converted by a holding circuit 100 such as a one-shot multivibrator into an MM synchronizing signal Z which has one pulse in every frame. A frame address counter 60 goes up in response to the MM synchronizing signal Z and output the common frame address A3 of respective tracks. Thus, reproduced data which are S/P-converted, word by word, by S/P converters 51, 52...5n are stored in specific addresses of RAMs 81, 82...8n with the common frame address A3 of respective tracks and individual word addresses A2 of the tracks. |
