| 摘要 |
An analog to digital converter uses an integrator having an input to which is applied the unknown voltage to be converted. An opposing reference voltage is switched by a switch means between positive and negative levels to cause the integrator output to ramp up and down between two levels to produce a periodic sawtooth waveform. The sawtooth waveform is applied to a hysteresis comparator which changes its output state when the sawtooth wave form magnitude equals the upper and lower hyteresis levels of the comparator. The output of the comparator is arranged to trigger an edge-sensitive "D" flip-flop. A fixed frequency clock signal from a clock signal source is applied to a clock input of the flip-flop to switch the flip-flop in combination with the output from the comparator. An output signal from one side of the flip-flop is applied as an actuating signal to the switch means to switch the reference signal level. An output signal from the other side of the flip-flop as well as the clock output from the clock signal source is applied to a 3-input AND gate to be combined with an output from a frequency divider arranged to divide the clock signal by a predetermined number. Thus, the operation of the AND gate between its open and closed states is synchronized with the occurrence of the clock signal. The output signal from the AND gate representing the clock signals passed through the AND gate is applied to a counter to be counted. The total number of clock pulses counted during the time period during which the AND gate is open is representative of the amplitude of the input signal to be converted. The stored count from the counter is periodically read out by an output signal from a control circuit triggered by the output from the frequency dividing circuit.
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