| 摘要 |
A test pattern generator for providing test patterns to a logic circuit under test, wherein the logic circuit to be tested does not have a terminal for being set to an initial state before starting the test patterns. The initial state of the logic circuit is detected while supplying an increment pattern to increment the internal state, and the test patterns are supplied a predetermined number of clock pulses after the initial state is detected. The length of the period of the clock pulses for the test can be varied. |
