| 摘要 |
PURPOSE:To exclude a frame synchronizing fault due to pseudo locking by utilizing a parity bit included in a data signal string so as to discriminate a pseudo locking state and establishing the frame synchronization via both frame retrieval. CONSTITUTION:A frame pattern comparison circuit 9 comprising exclusive OR circuits 7, 8 compares the phase between a prescribed reception side frame synchronizing pattern and an input data signal. As a result, a detection circuit 11 detects coincidence/dissidence of the frame pattern. A parity count circuit 10 measures the parity to an input data signal string. A parity coincidence/ dissidence circuit 12 discriminates out of frame synchronism and outputs a prescribed level signal. A clock inhibition circuit 17 comprising an inhibition control circuit 14 and an inhibition circuit 15 outputs a clock signal at frame synchronization and inhibits the output of the clock signal at asynchronous state. A frame pattern timing signal generating circuit 16 generates a frame synchronizing pattern and a timing pulse. |
