| 摘要 |
PURPOSE:To shorten the access time and to attain a high-speed operation with a memory containing a redundant circuit, by supplying an address to a comparator from a signal production stage preceding the production stage for an internal address signal which is supplied to an address decoder. CONSTITUTION:A row address buffer 1 and a column address buffer 1b are provided to a dynamic RAM of an MOS type. Thus input address signals Axi and Ayi are converted into internal complementary address signals axi and -axi and ayi and -ayi respectively. While the signal Ayi is supplied to a column switch 7 of a memory array 6 via a column address buffer and decoders 1b and 2b. Then signals axi and -axi are supplied to a row address decoder 2a, and the complementary address signals axi' and -axi' obtained by converting the level of the signal Axi are applied to a comparator 3 which compares defective addresses. A selection signal phixij is applied to a selection signal producing circuit 4. The output of the circuit 4 controls drives 5 and 5s for word line and spare word line respectively to increase the access speed of the array 6. |
