CIRCUIT FOR EXTRACTING TIMING CLOCK

摘要

PURPOSE:To increase zero consecutive strength and jitter strength by providing an integration circuit integrating '0', '1' input signal and using the integration value to control the Q of the filter extracting the clock frequency component. CONSTITUTION:An inputted digital signal is subject to equalization of attenuation distortion and waveform distortion by a line at an equalizing amplifier 1, amplified by an identification circuit 2 and a timing preamplifier 3, given to a timing wave generating circuit of the next stage to generate a timing wave. The level of the input signal is integrated by an integration circuit 6, the integration value is given to an FET7 to change the internal resistance of the FET7 thereby changing the sum between the resistance R and the internal resistance of the FET7. Further, the strength against consecutive 0s and the strength of an input signal against jitter are increased by increasing the Q of the filter 4 extracting the clock frequency component.