| 摘要 |
PURPOSE:To minimize the phase error between an input signal and a synchronizing signal by balancing the detected output of a synchronous detection circuit so as to reduce a phase error of an output synchronizing signal of a PLL circuit. CONSTITUTION:An input signal is subjected synchronous detection 5, 6 by using an output signal having a nearly 90 deg. of phase difference with the input signal outputted from a phase locked circuit section having a phase comparator 1 outputting a signal in response to a phase difference between the input signal and the output signal and a voltage controlled oscillator 3 oscillated in a frequency in response to the output signal. The DC component is also zero in the output of a 90 deg. phase detecting circuit 6 when the phase error is zero. When a phase error exists conversely, the DC component in response to the error is outputted. Then the output of the circuit 6 offsets the output of the phase comparator 1 and the phase error is zeroed by controlling the PLL circuit so as to zero the DC component of the output of the 90 deg. synchronous detection circuit. |
