| 摘要 |
An information processing apparatus employs first and second direct memory access controllers which cooperate during transfer of information between first and second devices, e.g. memories. The first controller controls information transfer from the first memory to the second controller and the second controller transfers the information from its own internal storage to the second memory while simultaneously receiving further information under the control of the first controller. The second controller includes address control circuitry for high speed generation of non-sequential addresses for writing into the second memory. |
