PROCESS FOR FABRICATING A HIGH SPEED BIPOLAR TRANSISTOR

摘要

The process employs ion implantation for precise dopant control. The implantation is performed into a thin layer of amorphous silicon covering the emitter and collector opening. The implantation energy is chosen so that the damage is confined to the amorphous layer. Since the deposited silicon layer is to be removed by subsequent processing, its thickness must be carefully controlled. The layer is preferably deposited by a sputtering technique which allows the necessary uniformity and reproducibility of the layer thickness. Furthermore, the sputtering process with its energetic ions provides a reproducible quality interface which is of critical importance for a diffusion source. With such a source, the diffusion into the single crystal silicon extends about the same distance in the horizontal as the vertical direction. This provides the greatest possible horizontal displacement of the junction under the passivating silicon dioxide layer. The depths of the n-type region is thinned to the single crystal surface by consuming the polysilicon partly through oxidation and partly through conversion to platinum silicide. The platinum silicide silicon interface provides a high surface recombination velocity in order to deplete the density of holes injected into the emitter. The low hole density in the emitter region has a direct benefit of decreasing the switching delay due to hole storage in the emitter, and hence higher device performance.