| 摘要 |
PURPOSE:To reduce the load of PU by modifying only the header part stored in a receiving buffer memory under the control of processor unit PU and transferring it to a transmission buffer memory and transferring directly the data part. CONSTITUTION:A received packet is stored in receiving buffer memory 11 from receiving HDLC (high-level data link control) circuit 4 temporarily. When recognizing receiving buffer completion, PU1 instructs DMAC (direct memory access) circuit 3 to transfer only the header part to memory 2 and modify it. After modification completion, PU1 instructs DMAC circuit 3 again to transfer the header part to transmission buffer memory 12 by DMA (direct memory access). Following this transfer, the data part stored in receiving buffer memory 11 is transferred to transmission buffer memory 12 by DMA under the control of DMAC circuit 3. |
