发明名称 Failsafe decision circuit
摘要 A decision circuit is responsive to digital input signals and to timing signals for reshaping and retiming the input signals into reshaped and retimed output signals. The decision circuit also is responsive to the digital input signals and absence of the timing signals for reshaping but not retiming the digital input signals into reshaped output signals which are transmitted. Thus the circuit produces and transmits reshaped output signals even upon failure to apply the timing signals required by a prior art decision circuit.
申请公布号 US4583007(A) 申请公布日期 1986.04.15
申请号 US19850775703 申请日期 1985.09.13
申请人 AT&T BELL LABORATORIES 发明人 PASKI, ROBERT M.
分类号 H03K3/2885;H03K5/12;H03K17/60;H04L25/06;H04L25/24;(IPC1-7):H03K5/01 主分类号 H03K3/2885
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