| 摘要 |
In a digital data processing system including an Instruction Unit, an Execute Unit, and a multilevel Processor Storage System including a cache memory, additional apparatus is included referred to as a Load Control Block Address Unit for implementing a load control block address instruction which permits prefetching of data from main memory into cache simultaneous with execution of a sequence of instructions in a linked list wherein information determining starting address of a next block in the linked list is stored at a location in the current block at a fixed offset from the beginning of the block.
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