| 摘要 |
PURPOSE:To optimize automatically the phase of synchronizing data and of a clock by providing an N-phase selecting part, phase comparing part, averaging part, phase advance/delay deciding part, and an UP/DOWN counting part. CONSTITUTION:A synchronizing clock demodulation part 2 outputs N clocks having different phases respectively and the N-phase selecting part 7 selects one of these clocks to read demodulated synchronizing data and detect synchronization. If synchronization can not be detected, a counter in the UP/DOWN counting part is counted up and the selection value of the selecting part 7 is changed to select the succeeding clock and detect its synchronization. When the synchronization coincides with a constant synchronizing pattern after the detection of the synchronization, the rise of the selected clock is compared with a time up to the changing point of the synchronizing data by the phase comparing part and a level AM selected on the basis of a value counted by an NCK is outputted from a level selecting part 13. If coincidence is not obtained, jitter is removed by the averaging pat 14 and the jitter-removed signal is inputted to the phase advance/delay deciding part 15. Then, the phase is optimized by the selecting part 7, the UP/DOWN counter 8 and a phase compensation counting part 11 on the basis of the decided result of the decision part 15. |
