| 摘要 |
PURPOSE:To attain the transfer of data at a high speed by producing plural read addresses in response to read start addresses to output the corresponding read data and at the same time sending plural answer signals back to a transmission strobe in response to the data output. CONSTITUTION:A memory element 20 receives the start address on an address bus A-BUS and the address of lower 2 bits from an address counter 25 via a receiver 23 and performs an access. Thus the corresponding data is sent to a data bus D-BUS from the memory 20. At the same time, a memory control part 22 produces an answer signal SRVO through a memory access control part 22b and outputs it to an answer signal line C1. Then a counter 22a which counts the output frequencies of the answer signals for each strobe and the counter 25 are counted up in a memory 2, and an access is given to the next word of the element 20. Thus the count value of the counter 22a reaches '4', and the data are delivered four times. In other words, the answer signals are delivered four times. Thus the part 22b stops the access of the element 20. |
