| 摘要 |
PURPOSE:To detect a stable frame synchronizing signal by ANDing a frame synchronizing signal detected from an input data string and a delay output shifting the said signal at each unit of frame to eliminate noises. CONSTITUTION:The data string including the frame synchronizing signal inputted to a terminal 1 is inputted to a shift register 3, outputted in parallel in the unit of N bits by using a clock signal inputted to a terminal 2, inputted to a NAND gate circuit 4 by using a clock signal from a terminal 2, and the detected pulse is outputted at the frame synchronizing position. The output of the circuit 4 is inputted to a delay circuit 5 giving N-frame delay in the unit of frame and the delayed output is inputted to an elimination circuit 6. The circuit 6 ANDs outputs of the circuits 4, 5 to eliminate the noise other than the synchronizing signal and its output is given to a coincidence circuit 7 and a dissidence circuit 8. The circuits 7, 8 use a signal from a frame counter 12 to detect the coincidence/dissidence, and the number is counted respectively by counters 9, 10. When the number of counters 10 is less than the number of counters 9, a frame synchronizing signal is obtained at the output of the counter 12. |
