| 摘要 |
PURPOSE:To increase the processing speed by dividing the (i) column every prescribed plural columns among i-column and j-column component elements of a ladder sequence circuit and performing the parallel processing to the bit information successively and every row for the divided columns through a single central processor. CONSTITUTION:The j-column is divided every prescribed plural column Col among i-column and j-column component elements I and O for a ladder sequence. A bit showing the start of sequence and the relay contact information are fetched for each row (a) of the divided column or delivered. A control part containing a bit which discriminates the above-mentioned decision. Then an instruction including said control part, the 1st operation code part showing whether the input contact of the ladder sequence is equal to a contact A or B, the 2nd operation code part containing a bit which discriminates the presence or absence of the connection between adjacent columns Co and an input/output address part showing an input contact and the address of an output coil is stored in a memory. Then the bit information corresponding to ON and OFF of a contact are fetched for each row (a) of the divided column Col. The processing is carried out according to an instruction stored previously for each column Col divided every row (a). |
