| 摘要 |
PURPOSE:To obtain a digital signal without jitter by supervising always the state of a memory in use and controlling the frequency of a read clock in response to the state in use so as to use the memory always in normal state and control surely jitter component included in a reproduced digital signal. CONSTITUTION:The state in use in the memory 24 is supervised always by a memory controller 25, and when the memory 24 overflows or is idle (no data exists), the information representing the state is fed from the controller 25 to a voltage generator 6. The voltage generator 36 generates a positive control voltage when the memory 24 overflows and generates a negative control voltage when the memory 24 is idle depending on the information representing the state in use of the memory 24 from the memory controller 25, the voltage is superimposed on the output voltage of an LPF 32, the result is fed to a VCO 27 via a changeover switch 33 to control the frequency of the read clock. Thus, the memory 24 is kept to the normal state at all times. |
